1 tm file number 4778.2 hip1015, hip1015a, hip1016, hip1016a power distribution controllers the hip1015 and hip1016 families are hot swap power controllers. the hip1015 family is targeted for +12v control applications whereas the hip1016 family is targeted for +5v control applications. each has an undervolt age (uv) monitoring and reporting threshold level ~17% lower than the nominal +12v and +5v. the hip1015 family has an integrated charge pump allowing control of up to +12v using an external n-channel mosfet. the hip1016 can also be used to control much higher positive or negative volt ages in a low side controller configuration. both ic families feature programmable overcurrent (oc) detection, current regulation (cr) with time delay to latch off and soft start. the ?non a? vs. ?a? differentiation is in the functionality of the pgood feature, how and when it reports an uv condition. on both of the ?a? devices the pgood feature is always enabled once the ic is biased, monitoring and reporting a uv condition on the isen pin. the pgood feature on the ?non a? device is disabled during turn-on of the external mosfet until the gate pin voltage has reached a particular voltage. (see the spec table for detail) pgood is pulled up to vdd during this disabled period. tape and reel devices can be specified by the addition of a ?-t? suffix to the following part numbers. features hot swap single power distribution control (hip1015 for 12v, hip1016 for 5v and low side switch) 2 undervoltage monitoring and notification schemes (?non a? vs. ?a? devices) overcurrent fault isolation programmable current regulation level programmable current limit time to latch-off rail to rail common mode input voltage range (hip1015) internal charge pump allows the use of n-channel mosfet (hip1015) undervoltage and overcurrent latch indicators adjustable turn-on ramp protection during turn on two levels of overcurrent detection provide fast response to varying fault conditions 1 s response time to dead short applications power distribution control hot plug components and circuitry high side low voltage (< +15v) switching low side high voltage (> +15v, negative v) switch pinout hip1015, hip1016 (soic) top view ordering information part number temp. range ( o c) package pkg. no. hip1015cb 0 to 85 8 lead soic m8.15 HIP1015ACB 0 to 85 8 lead soic m8.15 hip1016cb 0 to 85 8 lead soic m8.15 hip1016acb 0 to 85 8 lead soic m8.15 iset isen gate vss 1 2 3 4 8 7 6 5 pwron pgood ctim vdd application one - high side controller application two - low side controller +12v - + pwron load pgood oc 1 2 3 4 8 7 6 5 hip1015 load 12v reg +vbus oc 1 2 3 4 8 7 6 5 pwron hip1016 data sheet may 2001 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001, all rights reserved
2 simplified block diagram pin descriptions + - i set i sen gate v ss v dd ctim pgood pwron clim woclim enable oc 10 a fall ing edge delay 18v + - v ref + - 1.86v 12v + - r r s qn q enable por v dd 8v rising edge pulse + - + - uv 18v 20 a 7.5k + - + - 20 a uv disable non ?a? pin # symbol function description 1 iset current set connect to the low side of the current sense resistor through the current limiting set resistor. this pin functions as the current limit programming pin. 2 isen current sense connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 gate external fet gate drive pin connect to the gate of the external n-channel mosfet. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to v dd +5v (hip1015) and to v dd (hip1016) by a 10 a current source. 4 vss chip return 5v dd chip supply 12v chip supply. this can be either c onnec ted directly to the +12v rail supplying the switched load voltage or to a dedicated v ss +12v supply. 6 ctim current limit timing capacitor connect a capacitor from this pin to ground. this capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). the duration of current limit time-out (in seconds) = 93k ? x c tim (farads). 7 pgood power good indicator indicates that the voltage on isen pin is within specification. p good is driven by an open drain n-channel mosfet and is pulled low when the output is not within specification. on the hip1015a and hip1016a, pgood is enabled once ic is properly biased. on the hip1015 and hip1016 the pgood function is disabled until the gate voltage is within +/-2.5v of vdd. 8 pwron power on pwron is used to control and reset the chip. the chip is enabled when pwron pin is driven high or is open. after a current limit time out, the chip is reset by a low level signal applied to this pin. this input has 20 a pull up capability. hip1015, hip1015a, hip1016, hip1016a
3 absolute maximum ratings t a = 25 o c thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +16v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +8v isen, pgood, pwron, ctim, iset. . . . . . . -0.3v to v dd + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5kv operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . . . +12v+/-15% temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. (see tech brief, #tb37 9.1 for details.) 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 12v, t a = t j = 0 o c to 85 o c, unless otherwise specified parameter symbol test conditions min typ max units iset current source i iset_ft 18.5 20 21.5 a iset current source i iset_pt t j = 15 o c to 55 o c192021 a current limit amp offset voltage vio_ft v iset - v isen -6 0 6 mv current limit amp offset voltage vio_pt v iset - v isen, t j = 15 o c to 55 o c-2 0 2mv current limit time-out threshold voltage c tim _vth ctim voltage 1.3 1.8 2.3 v gate response time to severe oc pd_woc_amp v gate to 10.8v - 100 - ns gate response time to overcurrent pd_oc_amp v gate to 10.8v 600 ns gate turn-on current i gate v gate to = 6v 8.4 10 11.6 a gate pull down current oc_gate_i_4v overcurrent 45 75 ma gate pull down current woc_gate_i_4v severe overcurrent 0.5 0.8 1.5 a hip1015 undervoltage threshold 12v uv_vth 9.2 9.6 10 v hip1015 undervoltage disabled 12v uv_vth_dis hip1015 only, gate voltage meas. v dd +1.9v v dd +2.5v v hip1015 gate high voltage 12vg gate voltage v dd +4.5v v dd +5v - v hip1016 undervoltage threshold 5v uv_vth 4.0 4.35 4.5 v hip1016 undervoltage disabled 5v uv_vth_dis hip1016 only, gate voltage meas. v dd -3v v dd -2.5v v hip1016 gate high voltage 5vg gate voltage v dd -1.5v v dd -v v dd supply current i vdd -35ma v dd por rising threshold v dd_por_l2h vdd low to high 7.8 8.4 9 v v dd por falling threshold v dd_por_h2l vdd high to low 7.5 8.1 8.7 v v dd por threshold hysteresis v dd_por_hys v dd_por_l2h - v dd_por_h2l 0.1 0.3 0.6 v pwron pull-up voltage pwrn_v pwron pin open 2.7 3.2 - v pwron rising thres hold pwr_vth 1.4 1.7 2.0 v pwron hysteresis pwr_hys 130 170 250 mv pwron pull-up current pwrn_i 9 17 25 a c tim charging current c tim _ichg0 v ctim = 0v 16 20 23 a c tim fault pull-up current 16 20 23 ma hip1015 isen current isen_5v_i 41 72 88 a hip1016 isen current isen_5v_i 100 145 170 a hip1015, hip1015a, hip1016, hip1016a
4 description and operation the hip1015 and hip1016 families are single power supply distribution controllers for generic hot swap applications. the hip1015 family is targeted for +12v switching applications whereas the hip1016 family is targeted for +5v applications as each has an undervolt age (uv) threshold level ~17% lower than the nominal + 12v and +5v, r espectively. the hip1015 and hip1016 features incl ude a highly accu rate programmable overcurrent (oc) detecting comparator, programmable current regulation (cr) with programmable time delay to latch off and programmable soft start turn-on ramp all set with a minimum of external passive components. the ic families also include severe overcurrent protection t hat immediately shuts down the mosfet switch s hould the load current cause the oc voltage threshold to exceed the programmed oc level by 150mv. additionally the hip1015 and hip1016 families have an uv indicator and an oc latch indicator. the functionality of the pgood feature is the ?non a? vs. ?a? differentiation. on both of the ?a? devices the p good feature is always enabled once the ic is biased, monitoring and reporting an uv condition on the isen pin. the pgood feature on the ?non a? devices is disabled during turn-on of the external mosfet until the gate pin voltage is +/-2.5v of vdd. pgood is pulled up to vdd during this disabled period. upon initial power up, the hip1015 or hip1016 can either isolate the voltage supply from the load by holding the external n-channel mosfet switch off or apply the supply rail voltage directly to the load for true hot swap capability. in either case the hip1015 and hip1016 turns on in a soft start mode protecting the supply rail from sudden in-rush current. the pwron pin must be pulled low for the device to isolate the power supply from the load by holding the external n-channel mosfet off, otherwise with the pwron pin held high or floating the hip1015 and hip1016 will be in true hot swap mode. at turn-on, the gate capacitor of the external n- channel mosfet is charged with a 10 a current source resulting in a programmable ramp (soft start turn-on). the internal hip1015 charge pump supplies the gate drive for the 12v s upply switch driving that gate to v dd +5v. the hip1016 gate drive voltage is limited to the chip bias voltage. load current passes through the external current sense resistor. when the voltage across the sense resistor exceeds the user programmed overcurrent voltage threshold value, (see table 1 for r iset programming resistor value and resulting nominal overcurrent threshold voltage, v oc ) the controller enters current regulation. at this time, the time-out capacitor, on c tim pin starts charging with a 20ua current source and the controller enters the current limit time to latch-off period. the length of the current limit time to latch-off period is set by the single external capacitor (see table 2 for ctim capacitor value and resulting nominal current limited time out to latch-off period.) placed from the ctim pin (pin 6) to ground. the programmed current level is held until either the oc event passes or the time out period expires. if the former is the case then the n-channel mosfet is fully enhanced and the c tim capacitor is discharged. once ctim charges to 1.87v, signaling that the time out period has e xpired an internal latch is set whereby the fet gate is quickly pulled to 0v turning off the n- channel mosfet switch, isolating the faulty load. the hip1015 and hip1016 respond to a severe overcurrent load (defined as a voltage across the sense resistor > 150mv over the oc vth set point) by immediately, driving the n- channel mosfet gate to 0v in 1 s. the gate voltage is then slowly ramped up turning on the n-channel mosfet to the programmed current limit level, this is the start of the time out period. upon an uv condition the pgood signal will pull low when tied high through a resistor to the logic or vdd supply. this pin is an uv fault indicator. for an oc latch off indication, monitor ctim, pin 6. this pin will rise rapidly from 1.9v to 12v once the time out period expires. the ic is reset after an oc latch-off condition by a low level on the pwron pin and is turned on by the pwron pin being driven high. application considerations during the soft start and the time-out delay periods w ith the ic in its current limit mode, the v gs of the external n-channel mosfet is reduced driving the mosfet switch into a (li near region) high r ds(on) state. strike a balance between these requirements to avoid periods when the external n-ch annel mosfets may be damaged or destroyed due to excessive internal power dissipation. refer to the mosfet soa information in the manufacturers data sheet. when driving particularly large capacitive loads a longer soft start time to prevent current regulation upon charg ing and a short cr time may offer the best application solution relative to reliability and fet mtf. physical layout of r sense resistor is critical to avoid the possibility of false overcurrent occurrences. ideally trace routing between the r sense resistors and the hip1015 and table 1. r iset resistor nominal oc vth 10k ? 200mv 4.99k ? 100mv 2.5k ? 50mv 750 ? 15mv note: nominal vth = r iset x 20 a. table 2. c tim capacitor nominal current limited period 0.022 f2ms 0.047 f4.4ms 0.1 f9.3ms note: nominal time-out period in seconds = c tim x 93k ? . hip1015, hip1015a, hip1016, hip1016a
5 hip1016 is direct and as short as possible with zero current in the sense lines. (see figure 1.) using the hip1016 as a -48v low side hot swap power controller to supply the required v dd , it is necessary to maintain the chip supply 12v above the -48v bus. this may be accomplished with a +12v regulator between the voltage rail and pin 5 (vdd). by using a regulator, the designer may ignore the bus voltage variations. however, a low-cost alternative is to use a zener diode (see figure 2 for typical 5a load control) this option is detailed below. note that in this configuration the pgood feature (pin 7) is not operational. biasing the hip1016 table 3 gives typical component values for biasing the hip1016 in a 48v application. the formulas and calculations deriving these values are also shown belo w. when using the hip1016 to control -48v, a zener diode may be used to provide the +12v bias to the chip. if a zener is used then a current limit resistor should also be used. several items must be taken into account when choosing values for the current limit resistor (r cl ) and zener diode (dd1): the variation of the v bus (in this case, -48v) the chip supply current needs for all functi onal c onditions the power rating of r cl . the current rating of dd1 formulas 1. sizing r cl : r cl = (v bus,min - 12) /i chip 2. power rating of r cl : p rcl = i c (v bus,max - 12) 3. dd1 current rating: i dd1 = (v bus,max - 12) /r cl example a typical -48v supply may vary from -36 to -72v. therefore, v bus,max = -72v v bus,min = -36v i chip = 15ma (max) sizing r cl : r cl = (v bus,min - 12) /i c r cl = (36 - 12)/0.015 r cl = 1.6k ? [typical value = 1.58k ? ] power rating of r cl : p rcl = i c (v bus,max - 12) p rcl = (0.015)(72 - 12) p rcl = 0.9w [typical value = 1w] dd1 current rating: i dd1 = ( vbus,max - 12)/ r cl i dd1 = (72 - 12)/1.58k ? i dd1 = 38ma [typical value = 12v rating, 50ma reverse current] correct to isen and current sense resistor incorrect figure 1. sense resistor pcb layout r iset v bus load 1 2 3 4 8 7 6 5 hip1016 pwron nc figure 2. -48v r cl dd1 12v 1.58k ? ? ? ? 1w 0.01 f 0.047 f 1.47k ? ? ? ? 0.005 1% 0.001 f 2k ? ? ? ? 1% huf7554s3s table 3. typical values for a -48v hot swap application symbol parameter r cl 1.58k ? , 1w dd1 12v zener diode, 50ma reverse current hip1015, hip1015a, hip1016, hip1016a
6 typical performance curves figure 3. vdd bias current figure 4. iset source current figure 5. c tim current source figure 6. c tim oc voltage threshold figure 7. uv threshold figure 8. gate charge current 4.5 4.0 3.5 3.0 2.5 2.0 0 20 30 50 80 100 temperature ( o c) 5.0 supply current (ma) 10 40 60 70 90 20.2 temperature ( o c) iset current ( a) 0 20 30 50 80 100 10 40 60 70 90 20.0 19.0 19.2 19.4 19.6 19.8 20.5 20.32 20.0 19.66 c tim = 0v, current source (ma) temperature ( o c) 0203050 80100 10 40 60 70 90 19.5 20.16 19.82 c tim - 0v 1.89 1.88 1.87 1.86 1.85 1.83 c tim oc voltage threshold (v) temperature ( o c) 0203050 80100 10 40 60 70 90 1.84 temperature ( o c) hip1015, 12v uv threshold (v) 0 20 30 50 80 100 10 40 60 70 90 hip1016, 5v uv threshold (v) 9.67 9.65 9.66 4.5 4.0 4.25 hip1016 hip1015 temperature ( o c) 0 20 30 50 80 100 10 40 60 70 90 gate charge current ( a) 9.6 9.7 9.8 9.9 10.0 10.1 10.2 hip1015, hip1015a, hip1016, hip1016a
7 figure 9. gate drive voltage, vdd = 12v figure 10. power on reset voltage threshold figure 11. hip1015 high side +12v turn-on figure 12. hip1016 high side +5v turn-on figure 13. +50v low side switching cgate = 100pf figure 14. -50v low side switching cgate = 1000p f typical performance curves (continued) 17.200 17.183 17.166 17.150 17.133 17.100 12.00 11.99 11.98 11.97 11.96 11.95 11.94 temperature ( o c) hip1016, gate drive (v) hip1015, gate drive (v) 0 20 30 50 80 100 10 40 60 70 90 17.116 power on reset (v) temperature ( o c) 0 20 30 50 80 100 10 40 60 70 90 8.0 8.5 8.1 8.2 8.3 8.4 vdd lo to hi vdd hi to lo 2ms/div. iout 2a/div. vgate 5v/div. vout 5v/div. pwron 5v/div. 0v vgate 2v/div. vout 1v/div. iout 2a/div. pwron 5v/div. 0v 1.0ms/div. 5ms/div. vdrain 10v/div. +50v pwron 5v/div. 0v 0v vgate 5v/div. iout 1a/div. 5ms/div. iout 1a/div. 0v 0v vgate 5v/div. en 5v/div. -50v vdrain 10v/div. hip1015, hip1015a, hip1016, hip1016a
8 hip1015eval1 board the hip1015eval1 is configured as a +12v high side switch controller with the oc latch-off level set at ~1.5a. (see figure 17. for hip1015eval1 schematic and table 4. for bom.) bias and load connection points are provided along with test points for each ic pin. also included with the hip1015eval1 board is one loose packed hip1016 for 5v bus switching evaluation. with the chip to be biased from the +12v bus being switched, through b2, gnd b5, the load connected between b3 and b4 and with jumper j1 installed the hip1015 can be evaluated. pwron pin pulls high enabling hip1015 if not driven low. with the 750 ? overcurrent voltage threshold set resistor (r2) the oc vth is set to 15mv and with the 10m ? sense resistor the hip1015eval1 has a nominal oc trip level of 1.5a. the 0.047 f delay time to latch-off capacitors results in a nominal 4.4ms before latch-off of outputs after an oc event. each hip1015eval1 board is shipped with a hip1015 installed and a loose packed hip1015a. hip1016eval1 board the hip1016eval1 is default configured as a negative voltage low side switch controller with a ~2.4a oc latch-off level. (see figure 18 for hip1016eval1 schematic and table 4 for bom and component description.) this basic configuration is capable of contr olling both larger positive or negative potential voltages with minimal changes. bias and load connection points are provided in addition to test points, tp1-8 for each ic pin. the terminals, j1 and j4 are for the bus voltage and return, respectively, with the more negative potential being connected to j4. with the load between terminals j2 and j3 the board is now configured for evaluation. the device is enab led through login, tp9 with a ttl signal. hip1016eval1 includes a level shifting circuit with an opto-coupling device for the p wron input so that standard ttl logic can be translated to the -v reference for chip control. when controlling a positive voltage, pwron can be accessed at tp8. the hip1016eval1 is provided with a high voltage linear regulator for convenience to provide chip bias from +/-24v to +/-350v. this can be removed and replaced with the zener & resistor bias scheme as discussed earlier. high voltage regulators and power discrete devices are no longer available from intersil but can be purchased from other semiconductor manufacturers. reconfiguring the hip1016eval1 board for increased oc latch-off can be done by changing the r sense and r iset resistor values as the provided fet is 75a rated. if evaluation at > 60v, an alternate fet must be chosen with an adequate bv dss . each hip1016eval1 board is shipped with a hip1016 installed and a loose packed hip1016a. figure 15. +350v low side switching cgate = 100p f figure 16. +350v low side switching cgate = 1000pf typical performance curves (continued) 2ms/div. +350v 0v iout 1a/div. vdrain 50v/div. vgate 5v/div. pwron 5v/div. 2ms/div. +350v 0v iout 1a/div. pwron 5v/div. vgate 5v/div. vdrain 50v/div. hip1015, hip1015a, hip1016, hip1016a
9 figure 17. hip1015eval1 high side switch application figure 18. hip1016eval1 negative voltage low side controller 5 6 8 7 4 3 2 1 hip1015 q1 r2 r3 c1 c2 r4 d1 r5 d2 jp1 v bias v+ b2 dd1 +12v c3 r1 load - + pwron 3.3v b1 b5 b3 b4 u1 5 6 8 7 4 3 2 1 hip1016 q2 r2 r7 c1 r5 d2 c3 r1 load dd1 3.3v +vbus -vbus ot1 r9 r8 hi j2 j3 lo r6 r11 r10 on off 0-5v u1 j1 j4 pwron tp8 login tp9 r g 1 table 4. bill of materials, hip1015eval1, hip1016eval1 component designator component name component description q1 huf76132sk8 intersil corp, huf76132sk8, 11.5m ? , 30v, 11.5a logic level n-channel ultrafet? power mosfet q2 huf7554s3s intersil corp, huf7554s3s, 10m ? , 80v, 75a n-channel ultrafet? power mosfet r1 load current sense resistor dale, wsl-2512 10m ? 1w metal strip resistor high side r2 overcurrent voltage threshold set resistor 750 ? 805 chip resistor (vth = 15mv) lowside r2 overcurrent voltage threshold set resistor 1.21k ? 805 chip resistor (vth = 24mv) c2 time delay set capacitor 0.047 f 805 chip capacitor (4.5ms) c1 gate timing capacitor 0.001 f 805 chip capacitor (<2ms) c3 ic decoupling capacitor 0.1 f 805 chip capacitor r3 gate stability resistor 20 ? 805 chip resistor r7 gate to drain resistor 2k ? 805 chip resistor jp1 bias voltage selection jumper install if switched rail voltage is = +12v+/-15%. remove and provide separate +12v bias voltage to u1 pin 5 if switched rail vol tage is lower t han 12v. r4, r5 led series resistors 2.32k ? 805 chip resistor d1, d2 fault indicating leds low current red smd led dd1 fault voltage dropping diode 3.3v zener diode, sot-23 smd 350mw ot1 pwron level shifting opto-coupler ps2801-1 nec r8 level shifting bias resistor 2.32k ? 805 chip resistor r9 level shifting bias resistor 1.18k ? 805 chip resistor r10 level shifting bias resistor 200 ? 805 chip resistor rg1 hip5600is high voltage linear regulator r6 linear regulator rf1 1.78k ? 805 chip resistor r11 linear regulator rf2 15k ? 805 chip resistor tp1-tp8 test points for device pin numbers 1-8 hip1015, hip1015a, hip1016, hip1016a ultrafet? is a registered trademark of intersil corporation
10 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at website www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is c autioned to verify that data sheets are current before placing orders. informat ion furni shed by inte rsil is believed to be accurate and reliable. how- ever, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resul t from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web sit e www.intersil.com sales office headquarters north america intersil corporation 2401 palm bay road palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 hip1015, hip1015a, hip1016, hip1016a small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0 .006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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